The present invention relates generally to a nonvolatile memory device and a method of manufacturing the nonvolatile memory device, and more particularly to a NAND flash memory device and a method of manufacturing the NAND flash memory device.
According to higher integration demands of a nonvolatile memory device and the decrease in pitch between memory cells, the defect rate when forming a pattern on the nonvolatile memory device has been increasing. Since it is advantageous to create highly integrated NAND flash memory devices, defects are easily generated when forming gate patterns.
A method of forming the gate pattern of the NAND flash memory device will be described below. First, a tunnel insulating layer and a charge storage layer are deposited on a semiconductor substrate. The charge storage layer, the tunnel insulating layer, and the semiconductor substrate are etched using an isolation hard mask patterns as etching barriers, forming trenches in a first direction in the semiconductor substrate. The tunnel insulating layer patterns and the first charge storage layer patterns remain on active regions of the semiconductor substrate divided by the trenches. The trenches are filled with an insulating material, to form an isolation layers.
The charge storing layer and a control gate layer may be formed in subsequent processes by increasing the facing area between the charge storing layer and the control gate layer. In order to improve the couple rate between the two layers, the height of the isolation layer is formed to be less than that of the first charge storage layer pattern through the etching process. Accordingly, the Effective Field oxide Height (EFH) of the isolation layer is determined and a part of the side wall of the first charge storage layer pattern is exposed.
A dielectric layer is formed along a surface of the first charge storage layer pattern of which a part of the side wall is exposed, and a surface of the isolation layer, and the control gate layer is subsequently formed on the dielectric layer. The control gate layer is formed with a thickness sufficient to fill a space between the first charge storage layer patterns. Subsequently, gate hard mask patterns in a second direction crossing the first direction are formed over the control gate layer. The control gate layer, the dielectric layer and the first charge storage layer patterns are etched using the gate hard mask patterns as etching barriers. Accordingly, the control gate layer patterns are formed as lines in the second direction, and each of the first charge storage layer patterns are divided into a plurality of second charge storage layer patterns at each of the active regions. The charge storage layer remains in a crossing part of the control gate layer pattern and the active region.
In a process of patterning the control gate layer, the dielectric layer, and the first charge storage layer patterns, the dielectric layer formed on the side wall of the first charge storage layer pattern is not completely removed and remains to form a fence. The fence of the dielectric layer blocks a part of the charge storage layer to be etched, so that an unnecessary part of the charge storage layer may not be removed. The second charge storage layer patterns are not isolated, but are connected through a remaining partial region of the charge storage layer through the fence of the dielectric layer on the active region, thereby causing failure of the device. During a process of injecting impurities in order to form a junction region, the impurities are not injected to a part of the active region adjacent to the partial region of the charge storage layer left due to the fence of the dielectric layer, thereby generating a disturbance during the operation of the device.